1. Field of the Invention
The present invention relates to a pattern verifying method, a pattern verifying device, a program, and a manufacturing method of a semiconductor device, in which a pattern used for a double patterning method is verified.
2. Description of the Related Art
In recent years, the semiconductor device has been miniaturized. As a technique for realizing the miniaturization exceeding a resolution limit of lithography, the double patterning method is largely expected. As described in Japanese Patent Laid-Open No. 2007-27742, the double patterning method is a method in which a pattern belonging to one layer is divided to two patterns, and each of the divided patterns is exposed and developed.
As another method which realizes the miniaturization of the semiconductor device, some technique uses a Levenson type phase shift mask. In this technique, a final pattern is obtained on a wafer by using two masks in which shapes of an aperture part and phase differences are different from each other. The resolutions are different from each other in the two patterns formed by the two masks. In a technique described in Japanese Patent Laid-Open No. 2007-310085, when a process simulation of the Levenson type phase shift mask is executed, an allowable margin is individually set for each of the two masks, the process simulation is executed by using the pattern of at least one of the two masks, and a result of the simulation is compared with the allowable margin.
When using such techniques, the inventor of the present application has newly known the following problems. As described above, the double patterning method is a method in which the pattern belonging to one layer is divided to the two patterns, and each of the divided patterns is exposed and developed. Thus, when an overlapping margin is induced in the divided patterns, parts to be normally connected may be separated, and parts to be normally divided may be connected. Thus, when the double patterning method is used, it is preferable to verify the pattern under consideration of the overlapping margin. However, in the techniques described in the above Patent Documents, it is not possible to verify the pattern under the consideration of the overlapping margin.